Digital Design Engineer

CDI to 100% immediately or to be agreed.

Postulation uniquement en ligne - merci de mentionner sous source (ORP)

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

We are actively seeking for a Digital Design Engineer
Location: Lausanne (St-Sulpice), Switzerland

Responsibility

Concept definition, analog to digital interface specification
RTL design with basics of Dft and IP verification
Logic synthesis, Timing analysis – desired
Close interaction with Verification engineers, Analog/Mixed signal designers
Develop block level specifications of very high-speed digital circuits that meet key performance targets based on system level requirement