Physical Design Engineer

Postulation uniquement en ligne - merci de mentionner sous source ORP.

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Job title: Advanced R&D - Physical Design Engineer

Location : Lausanne, Switzerland

The Physical Design (PD) Engineer translates high-speed communication IP digital designs into physical GDSII layouts for advanced FinFET nodes. You will bridge logic design, owning block-to-chip implementation from netlist to final physical sign-off, ensuring PPA (Power, Performance, and Area) targets are met.

Immediate key objective

Drive block-level physical implementation—covering synthesis, SDC constraints, floorplanning, placement, CTS, and routing—meeting strict frequency, area, and power targets.
Execute timing closure across multiple corners and modes (MCMM) utilizing static timing analysis (STA) and generating targeted ECOs.